The invention relates to the formation of silicon dioxide and silicon nitride dual dielectric structures of the type used in MNOS (metal-nitride-oxide-semiconductor) structures and, more particularly, to a process for forming memory-quality silicon dioxide and silicon nitride dual dielectric structures in the same deposition system.
In the past, the high quality silicon nitride films required in MNOS memory technology have been obtained principally by the atmospheric chemical vapor deposition technique. (Note, as used here, MNOS includes silicon gate structures, SNOS.) In the last few years there has been increasing interest in low pressure chemical vapor deposition of silicon nitride using reactants such as ammonia (NH.sub.3) and dichlorosilane (SiCl.sub.2 H.sub.2) or silane (SiH.sub.4). As discussed, for example, in the Journal of Vacuum Science Technology, Vol. 14, No. 5, September/October 1977 page 1089, surface reaction is the rate determining factor in the low pressure technique rather than mass transfer, which is critical in atmospheric pressure techniques. Elimination of mass-transfer variables and such constraints as reactor configuration permits optimization of reactor design for temperature uniformity and wafer throughput. Consequently, the low pressure process typically uses a resistance-heated tube furnace to take advantage of the uniform temperatures and the large potential throughput (provided by the large deposition zones as well as the close-packed vertical wafer loading) of such furnaces.
It is highly desirable to more fully utilize these advantages during the formation of memory MNOS structures by forming the silicon dioxide dielectric as well as the silicon nitride dielectric in the same furnace tube using essentially a continuous process. Such a process would avoid the time lost in transferring wafers between deposition systems. This includes time lost in reducing the oxidation system temperature to near-room temperature prior to removal of the wafer(s) from the oxidation system, transferring the wafers to the nitride deposition system, and then raising the temperature of the nitride deposition system. Another factor is the possible change and/or degradation in oxide characteristics due to the elongated exposure to elevated temperatures, in oxidizing and/or impurity-containing atmosphere. Perhaps more importantly, using the same furnace tube to form the oxide and the nitride would avoid or prevent Si--SiO.sub.2 --Si.sub.3 N.sub.4 interface contamination.
Full utilization of the potential advantages of forming the oxide and nitride in the same furnace tube requires that the two dielectrics be formed at, or near, the same temperature, to eliminate the long stabilization times characteristic of resistance-heated furnaces and thereby both save time and avoid prolonged exposure of the silicon dioxide layer to the furnace atmosphere.
Unfortunately, using the same temperature for the silicon dioxide and silicon nitride formation involves different, frequently conflicting, problems and considerations. First, the thin (e.g. 15-25 Angstroms 1.5-2.5 nanometer, nm) memory oxide must be formed at a relatively low temperature because growth at elevated temperatures would be too rapid for adequate control of thickness.
Secondly, low silicon nitride formation temperatures are also desirable, to reduce mechanical stresses caused by the different thermal expansions of silicon and silicon nitride and to provide the proper memory retention characteristics of the film, such as the density and energy position of the charge trapping centers in the nitride.
Another consideration is applicable to MNOS formation in general, viz., that the use of elevated temperatures in forming the silicon dioxide and the silicon nitride can adversely affect existing structure. For example, high temperatures can modify or degrade existing logic gates and FET structures and/or cause migration of existing impurity regions such as sources and drains. Note also that in the case of the silicon nitride formation these existing structures include the thin silicon dioxide memory gate dielectric.
Unfortunately, a countervailing consideration is that low temperatures not only cause poor stoichiometry and high Q.sub.SS (because of longer oxidation times at lower temperatures) for the silicon substrate-silicon dioxide interface, but also give lower growth rates and lesser quality silicon nitride.